Collaborators Anand Raghunathan NEC Labs Publications A Power Management Methodology for High-Level Synthesis A Scalable Software-Based Self-Test Methodology for Programmable Processors, Adaptation of Video Encoding to Address Dynamic Thermal Management Effects An Application Adaptation Approach to Mitigate Impact of Dynamic Thermal Management on Video Encoding Battery Life Estimation for Mobile Embedded Systems Battery-Driven System Design: A New Frontier in Low Power Design Battery-Efficient Architecture for an 802.11 MAC Processor Common-case computation: A high-level power optimization technique Communication Architecture Based Power Management for Battery-Efficient System Design Communication Architecture Tuners: A Methodology for the Design of High-Performance Communication Architectures for System-on-Chip Communication Based Power Management Considering Process Variations during System Level Power Analysis Controller Re-specification to Minimize Switching Activity in Controller/Data Path Circuits Design of Communication Architectures for High-Performance and Energy-Efficient System-on-Chips Design of High-Performance System-on-Chips using Communication Architecture Tuners Design Space Exploration for Optimizing On-Chip Communication Architectures Efficient Exploration of the SoC Communication Architecture Design Space Efficient Power Co-Estimation Techniques for Systems-on-Chip Design Efficient Power Estimation Techniques for HW/SW Systems Efficient Power Profiling for Battery-Driven Embedded System Design Energy Modeling for Wireless Internet Access Evaluation of the Traffic-Performance Characteristics of System-on-Chip Communication Architectures Fast Performance Analysis of Bus-based System-on-Chip Communication Architectures Fast System-Level Power Profiling for Battery-Efficient System Design FLEXBUS: A High Performance System-on-Chip Communication Architecture with a Dynamically Configurable Topology Glitch Analysis and Reduction in Register Transfer Level Power Optimization High Level Power Analysis and Optimization High-Level Macro-Modeling and Estimation Techniques for Switching Activity and Power Consumption Integrated Data Relocation and Bus Reconfiguration for Adaptive SoC Platforms Joint Work and Voltage/Frequency Scaling for Quality-Optimized Dynamic Thermal Management LOTTERYBUS: A New High-Performance Communication Architecture for System-on-Chip Designs Network Aware Content Shaping for Energy Efficient Wireless Web Access Performance Analysis of Systems with Multi-Channel Communication Architectures Power Management in High Level Synthesis Power Management Techniques for Control-Flow Intensive Designs Register-Transfer Level Estimation Techniques for Switching Activity and Power Consumption Register-Transfer-Level Power Estimation Techniques for Control-Flow Intensive Designs System-Level Performance Analysis for Designing On-Chip Communication Architectures System-on-chip Power Management Considering Leakage Process Variations Transforming control-flow intensive designs to facilitate power management Variation-aware System-level Power Analysis Variation-Tolerant Dynamic Power Management at the System-Level
