Low Power Embedded Nanochips

2012

  • A. Mirtar, S. Dey, and A. Raghunathan "Adaptation of Video Encoding to Address Dynamic Thermal Management Effects", Green Computing Conference (IGCC), 2012 International , vol., no., pp.1-10, 4-8 June 2012    PDF    IEEE_Explore

2007

  • S.Chandra, K.Lahiri, A.Raghunathan, S.Dey, "System-on-chip Power Management Considering Leakage Process Variations", in Proc. Design Automation Conference (DAC),2007.

2006

  • S.Chandra, K.Lahiri, A.Raghunathan, S.Dey, "Considering Process Variations during System Level Power Analysis", in Proc. International Symposium on Low Power Electronics and Design (ISLPED), pp. 342-345, October 2006.

2002

  • K.Lahiri, A.Raghunathan, S.Dey, D.Panigrahi, "Battery-Driven System Design: A New Frontier in Low Power Design", in Proc. Intl. Conf. on VLSI Design/ASP-DAC, pp.261-267, Bangalore, January 2002.
  • K.Lahiri, A.Raghunathan, S.Dey, "Communication Architecture Based Power Management for Battery-Efficient System Design", in Proc. Design Automation Conf., pp.691-696, New Orleans, June 2002 (Among 5 papers chosen as the Best of DAC in Practice).
  • K.Lahiri, A.Raghunathan, S.Dey, "Communication Based Power Management", IEEE Design and Test of Computers, vol.19, no.4, pp.118-130, July-August 2002. (appears in Special DAC Section).
  • C.N.Taylor, D.Panigrahi, S.Dey, "Design of an Adaptive Architecture for Energy Efficient Wireless Image Communication", Lecture Notes in Computer Science, vol.2268, pp.260-273, Springer-Verlag, 2002.
  • K.Lahiri, A.Raghunathan, S.Dey, "Fast System-Level Power Profiling for Battery-Efficient System Design", in Proc. Intl. Symp. HW/SW Co-design, pp.157-162, Estes Park, May 2002.
  • Mirtar, A; Dey, S.; Raghunathan, A, "Joint Work and Voltage/Frequency Scaling for Quality-Optimized Dynamic Thermal Management," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on , vol.PP, no.99, pp.1,1    IEEE Xplore
  • S.Chandra, K.Lahiri, A.Raghunathan, and S.Dey, "Variation-aware System-level Power Analysis", IEEE Trans. VLSI Systems. (to appear).

2001

  • D.Panigrahi, C.Chiasserini, S.Dey, R.Rao, A.Raghunathan, K.Lahiri, "Battery Life Estimation for Mobile Embedded Systems", in Proc. Intl. Conf. on VLSI Design, pp.55-63, Bangalore, January 2001.
  • D.Panigrahi, A.Raghunathan, G.Lakhsminarayana, S.Dey, "Energy Modeling for Wireless Internet Access", in Proc. Intl. Conf. on Third Generation Wireless and Beyond, San Francisco, pp.332-337, May 2001.
  • C.N.Taylor, S.Dey, Y.Zhao, "Modeling and Minimization of Interconnect Energy Dissipation in Nanometer Technologies", in Proc. Design Automation Conf., pp. 754-757, June 2001.

1999

  • G.Lakshminarayana, A.Raghunathan, K.S.Khouri, N.K.Jha, S.Dey, "Common-case computation: A high-level power optimization technique", in Proc. Design Automation Conf., June 1999.(Best Paper Award)
  • M.Lajolo, A.Raghunathan, S.Dey, L.Lavagno, A. Sangiovanni-Vincentelli, "Efficient Power Estimation Techniques for HW/SW Systems," in Proc. IEEE VOLTA, March 1999.
  • G.Lakshminarayana, A.Raghunathan, N.K.Jha, S.Dey, "Power Management in High Level Synthesis", IEEE Trans. on VLSI Systems, March 1999.

1998

  • G.Lakshminarayana, A.Raghunathan, N.K.Jha, S.Dey, "A Power Management Methodology for High-Level Synthesis," in Proc. Intl. Conf. on VLSI Design, January 1998 (Best Paper Award).
  • G.Lakshminarayana, A.Raghunathan, N.K.Jha, S.Dey, "Transforming control-flow intensive designs to facilitate power management", in Proc. Intl. Conf. on Computer-Aided Design, November 1998.

1997

  • A.Raghunathan, N.K.Jha, S.Dey, "High Level Power Analysis and Optimization", Kluwer Academic Publishers, Boston, MA, November 1997.
  • A.Raghunathan, S.Dey, N.K.Jha, K.Wakabayashi, "Power Management Techniques for Control-Flow Intensive Designs," in Proc. Design Automation Conf., June 1997.
  • A.Raghunathan, S.Dey, N.K.Jha, "Register-Transfer-Level Power Estimation Techniques for Control-Flow Intensive Designs," in Proc. Design Automation Conf., June 1997.

1996

  • A. Mirtar, S. Dey, A. Raghunathan "An Application Adaptation Approach to Mitigate Impact of Dynamic Thermal Management on Video Encoding", ACM Transactions on Design Automation of Electronic Systems (TODAES), Accepted.
  • A.Raghunathan, S.Dey, N.K.Jha, K.Wakabayashi, "Controller Re-specification to Minimize Switching Activity in Controller/Data Path Circuits," in Proc. Intl. Symp. on Low Power Electronics and Design, August 1996.
  • A.Raghunathan, S.Dey, N.K.Jha, "Glitch Analysis and Reduction in Register Transfer Level Power Optimization," in Proc. Design Automation Conf., June 1996.
  • A.Raghunathan, S.Dey, N.K.Jha, "Register-Transfer Level Estimation Techniques for Switching Activity and Power Consumption," in Proc. Intl. Conf. on Computer-Aided Design, November 1996.

1995

  • M.Potkonjak, P.Ashar, S.Dey, T.Misawa, R.K.Roy, "Synthesis techniques for low power digital systems," NEC Research and Development Journal, vol.36, No.1, pp.83-102, January, 1995.
  • G.Lakshminarayana, A.Raghunathan, K.S.Khouri, N.K.Jha, S.Dey, "Common Case Computation: A New Paradigm for Energy and Performance Optimization", to appear in IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems.
  • A.Raghunathan, S.Dey, N.K.Jha, "High-Level Macro-Modeling and Estimation Techniques for Switching Activity and Power Consumption", to appear, IEEE Trans. on VLSI Systems.
  • S.Chandra, K.Lahiri, A.Raghunathan, and S.Dey, "Variation-Tolerant Dynamic Power Management at the System-Level", IEEE Trans. VLSI Systems. (to appear).