2022

  • B. Kutukcu, S. Baidya, A. Raghunathan, and S. Dey. "Contention Grading and Adaptive Model Selection for Machine Vision in Embedded Systems", accepted in ACM Trans. Embedd. Comput. Syst.    PDF    ACM Digital Library

     

2021

  • B. Kutukcu, S. Baidya, A. Raghunathan, S. Dey, "Contention-aware Adaptive Model Selection for Machine Vision in Embedded Systems", in Proc. of 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS 2021), June 2021.    PDF    IEEE Xplore

     

2005

  • K.Sekar, K.Lahiri, A.Raghunathan, S.Dey, "FLEXBUS: A High Performance System-on-Chip Communication Architecture with a Dynamically Configurable Topology", in Proc. Design Automation Conf., pp. 571-574, Anaheim, June 2005

     

2004

  • K.Sekar, K.Lahiri, S.Dey, "Configurable Platforms With Dynamic Platform Management: An Efficient Alternative to Application-Specific System-on-Chips", Proc. International Conference on VLSI Design, Mumbai, India, Jan 2004

     

  • K.Lahiri, S.Dey, A.Raghunathan, "Design of Communication Architectures for High-Performance and Energy-Efficient System-on-Chips", book chapter, in Multiprocessor Systems-on-Chips , Morgan Kaufmann, September 2004.

     

  • K.Lahiri, A.Raghunathan, S.Dey, "Design of High-Performance System-on-Chips using Communication Architecture Tuners", IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol.23, no.5, pp. 620-636, May 2004

     

  • K.Lahiri, A.Raghunathan, S.Dey, "Design Space Exploration for Optimizing On-Chip Communication Architectures", IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol.23, no.6, June 2004. 

     

  • K.Lahiri, A.Raghunathan, S.Dey, "Efficient Power Profiling for Battery-Driven Embedded System Design", IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems , vol.23, no.6, June 2004.

     

2003

  • K.Sekar, K.Lahiri, S.Dey, "Dynamic Platform Management for Configurable Platform-Based System-on-Chips", Proc. International Conference on Computer-Aided Design, pp. 641-648, San Jose, Nov 2003.

     

2002

  • D.Panigrahi, C.N.Taylor, S.Dey, "A Hardware/Software Reconfigurable Architecture for Adaptive Wireless Image Communication", in Proc. Intl. Conf. on VLSI Design/ASP-DAC, pp.553-558, Bangalore, January 2002.

     

  • K.Lahiri, A.Raghunathan, S.Dey, "Battery-Efficient Architecture for an 802.11 MAC Processor", in Proc. Intl. Conf. on Communications, vol.2, pp.669-677, New York, April 2002.

     

  • K.Sekar, K.Lahiri, S.Dey, "Dynamically configurable bus topologies for high-performance on-chip communication", to appear in IEEE Transactions on VLSI.

     

2001

  • K.Lahiri, A.Raghunathan, S.Dey, "Evaluation of the Traffic-Performance Characteristics of System-on-Chip Communication Architectures", in Proc. Intl. Conf. on VLSI Design, pp.21-35, Bangalore, January 2001.

     

  • K.Lahiri, A.Raghunathan, G.Lakshminarayana, "LOTTERYBUS: A New High-Performance Communication Architecture for System-on-Chip Designs", in Proc. Design Automation Conf, pp.15-20, Las Vegas, June 2001.

     

  • K.Lahiri, A.Raghunathan, S.Dey, "System-Level Performance Analysis for Designing On-Chip Communication Architectures", IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no.6, pp.768-783, June 2001.

     

2000

  • K.Lahiri, G.Lakshminarayana, A.Raghunathan, S.Dey, "Communication Architecture Tuners: A Methodology for the Design of High-Performance Communication Architectures for System-on-Chips", in Proc. Design Automation Conf., pp.513-518, Los Angeles, June 2000 (Best Paper Award).

     

  • K.Lahiri, A.Raghunathan, S.Dey, "Efficient Exploration of the SoC Communication Architecture Design Space", in Proc. Intl. Conf. on Computer-Aided Design, pp.424-430, San Jose, November 2000.

     

  • M.Lajolo, A.Raghunathan, S.Dey, L.Lavagno, "Efficient Power Co-Estimation Techniques for Systems-on-Chip Design", in Proc. Design Automation and Test in Europe, Paris, March 2000.

     

  • K.Lahiri, A.Raghunathan, S.Dey, "Performance Analysis of Systems with Multi-Channel Communication Architectures", in Proc. Intl. Conf. on VLSI Design, pp.530-537, Calcutta, January 2000.

     

1999

  • K.Lahiri, A.Raghunathan, S.Dey,"Fast Performance Analysis of Bus-based System-on-Chip Communication Architectures", in Proc. Intl. Conf. on Computer-Aided Design, pp.566-572, San Jose, November 1999.