Interconnect Coupling-Aware Driver Modeling in Static Noise Analysis for Nanometer Circuits, Read more about Interconnect Coupling-Aware Driver Modeling in Static Noise Analysis for Nanometer Circuits,
Software-Based Self-Test Methodology for Crosstalk Faults in Processors, Read more about Software-Based Self-Test Methodology for Crosstalk Faults in Processors,
Abstraction of Word-level Linear Arithmetic Functions from Bit-level Component Descriptions, Read more about Abstraction of Word-level Linear Arithmetic Functions from Bit-level Component Descriptions,
Fault Modeling and Simulation for Crosstalk in System-on-Chip Interconnects Read more about Fault Modeling and Simulation for Crosstalk in System-on-Chip Interconnects
Constraint-Aware Robustness Insertion for Optimal Noise-Tolerance Enhancement in VLSI Circuits, Read more about Constraint-Aware Robustness Insertion for Optimal Noise-Tolerance Enhancement in VLSI Circuits,
Soft Spot Analysis: A Scalable Methodology Targeting Compound Noise Effects in Nano-meter Circuits Read more about Soft Spot Analysis: A Scalable Methodology Targeting Compound Noise Effects in Nano-meter Circuits
High-level Crosstalk Defect Simulation Methodology for System-on-Chip Interconnects, Read more about High-level Crosstalk Defect Simulation Methodology for System-on-Chip Interconnects,
A Scalable Soft Spot Analysis Methodology for Compount Noise Effects in Nano-meter Circuits Read more about A Scalable Soft Spot Analysis Methodology for Compount Noise Effects in Nano-meter Circuits
On-line testing of multi-source noise-induced errors on the interconnects and buses of system-on-chips Read more about On-line testing of multi-source noise-induced errors on the interconnects and buses of system-on-chips
ATPG for Crosstalk using Hybrid Structural SAT, Read more about ATPG for Crosstalk using Hybrid Structural SAT,
Fault Coverage Analysis Techniques of Crosstalk in Chip Interconnects, Read more about Fault Coverage Analysis Techniques of Crosstalk in Chip Interconnects,
Separate Dual Transistor Registor-an Circuit Solution for on-line Testing of Transient Errors in UDSM-IC, Read more about Separate Dual Transistor Registor-an Circuit Solution for on-line Testing of Transient Errors in UDSM-IC,
A Scalable Software-Based Self-Test Methodology for Programmable Processors, Read more about A Scalable Software-Based Self-Test Methodology for Programmable Processors,
On-line Testing for Multi-source Noise-induced Errors in System-on-Chip Interconnects and Buses, Read more about On-line Testing for Multi-source Noise-induced Errors in System-on-Chip Interconnects and Buses,
Embedded Software-Based Self-Test for Programmable Core-Based Designs, Read more about Embedded Software-Based Self-Test for Programmable Core-Based Designs,
Embedded Software-Based Self-Testing for SoC Design, Read more about Embedded Software-Based Self-Testing for SoC Design,
LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and Interconnects, Read more about LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and Interconnects,
Design for Verification at the Register Transfer Level Read more about Design for Verification at the Register Transfer Level
Testing for interconnect crosstalk defects using on-chip embedded processor cores, Read more about Testing for interconnect crosstalk defects using on-chip embedded processor cores,
High-level Crosstalk Defect Simulation for System-on-Chip Interconnects Read more about High-level Crosstalk Defect Simulation for System-on-Chip Interconnects
Software-Based Self-Testing Methodology for Processor Cores, Read more about Software-Based Self-Testing Methodology for Processor Cores,
Analysis of Interconnect Crosstalk Defect Coverage of Test Read more about Analysis of Interconnect Crosstalk Defect Coverage of Test
Interface Based Hardware/Software Validation of a System-on-Chip, Read more about Interface Based Hardware/Software Validation of a System-on-Chip,
Using a Soft Core in a SOC Design: Experiences with PicoJava, Read more about Using a Soft Core in a SOC Design: Experiences with PicoJava,
Embedded Hardware and Software Self-Testing Methodologies for Processor Cores, Read more about Embedded Hardware and Software Self-Testing Methodologies for Processor Cores,
Self-Test Methodology for At-Speed Test of Crosstalk in Chip Interconnects Read more about Self-Test Methodology for At-Speed Test of Crosstalk in Chip Interconnects
Test Challenges for Deep Sub-Micron Technologies Read more about Test Challenges for Deep Sub-Micron Technologies
DEFUSE: A Deterministic Functional Self-Test Methodology for Processors, Read more about DEFUSE: A Deterministic Functional Self-Test Methodology for Processors,
A Deterministic Functional Self-Test Methodology for Processors Read more about A Deterministic Functional Self-Test Methodology for Processors
Efficient transient error effects in digital nanometer circuits Read more about Efficient transient error effects in digital nanometer circuits
Evaluating and Improving Transient Error Tolerance of CMOS Digital VLSI Circuits Read more about Evaluating and Improving Transient Error Tolerance of CMOS Digital VLSI Circuits
Improving Transient Error Tolerance of Digital VLSI Circuits Using RObustness COmpiler (ROCO) Read more about Improving Transient Error Tolerance of Digital VLSI Circuits Using RObustness COmpiler (ROCO)
A Static Noise Impact Analysis Methodology for Evaluating Transient Error Effects in Digital VLSI Circuits Read more about A Static Noise Impact Analysis Methodology for Evaluating Transient Error Effects in Digital VLSI Circuits
An Intelligent Robustness Insertion Methodology for Optimal Transient Error Tolerance Read more about An Intelligent Robustness Insertion Methodology for Optimal Transient Error Tolerance
Modeling Soft Error Effects Considering Process Variations Read more about Modeling Soft Error Effects Considering Process Variations
