2007

  • Chong Zhao, Sujit Dey, "Modeling Soft Error Effects Considering Process Variations," to appear in International Conference on Computer Design (ICCD), October 2007, Lake Tahoe, California. 

2006

  • Chong Zhao, Sujit Dey, "Evaluating and Improving Transient Error Tolerance of CMOS Digital VLSI Circuits," in Proceedings of the International Test Conference 2006 (ITC), pp.29.1, October 2006, Santa Clara, California. 
  • Chong Zhao, Sujit Dey, "Improving Transient Error Tolerance of Digital VLSI Circuits Using RObustness COmpiler (ROCO)", in Proceedings of 7th International Symposium on Quality Electronic Design (ISQED), pp. 133-138, March 2006, San Jose, California, USA. Best Paper Award

2005

  • Chong Zhao, Xiaoliang Bai, Sujit Dey, "A Static Noise Impact Analysis Methodology for Evaluating Transient Error Effects in Digital VLSI Circuits", in Proceedings of International Test Conference 2005, pp. 40.2, October, 2005, Austin, Texas, USA.
  • Chong Zhao, Yi Zhao, Sujit Dey, "Constraint-Aware Robustness Insertion for Optimal Noise-Tolerance Enhancement in VLSI Circuits," in Proceedings of 42nd Design Automation Conference, pp. 190-195, June 2005, Anaheim, California, USA.
  • Chong Zhao, Xiaoliang Bai, Sujit Dey, "Soft Spot Analysis: A Scalable Methodology Targeting Compound Noise Effects in Nano-meter Circuits", IEEE Design & Test of Computers, VOL. 22, NO. 4, July-Aug. 2005, pp. 362-375.

2004

  • Chong Zhao, Xiaoliang Bai, Sujit Dey, "A Scalable Soft Spot Analysis Methodology for Compount Noise Effects in Nano-meter Circuits", DAC'04, San Diego, California, June 7-11, 2004.
  • Xiaoliang Bai, Sujit Dey, "High-level Crosstalk Defect Simulation Methodology for System-on-Chip Interconnects," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol 23, NO. 9, September 2004. pp. 1355~1361.
  • Xiaoliang Bai, Rajit Chandra, Sujit Dey and P. V. Srinivas, "Interconnect Coupling-Aware Driver Modeling in Static Noise Analysis for Nanometer Circuits," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 23, NO. 8, August 2004. pp. 1256~1263.

2003

  • L.Chen, S.Ravi, A.Raghunathan, S.Dey, "A Scalable Software-Based Self-Test Methodology for Programmable Processors," in Proc.Design Automation Conf., pp. 548-553, Anaheim, CA, June 2003 (Best Paper Award Candidate).
  • X.Bai, S.Dey, A.Krstic, "ATPG for Crosstalk using Hybrid Structural SAT," in Intl. Test Conference, pp.112-121, Charlotter, Oct. 2003.
  • Y.Zhao, S.Dey, "Fault Coverage Analysis Techniques of Crosstalk in Chip Interconnects," in IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 22, No. 6, pp.770-782, June 2003.
  • K.Sekar, S.Dey, "LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and Interconnects," Journal of Electronic Testing: Theory and Applications, vol.19, no.2, pp.113-123, April 2003.
  • X.Bai, R.Chandra, S.Dey, P.V.Srinivas, "Noise-Aware Driver Modeling", Proc. of the Intl. Symp.on Quality Electronic Design, pp.177-182, San Jose, March 2003.
  • Y. Zhao, L. Chen, S. Dey, "On-line testing of multi-source noise-induced errors on the interconnects and buses of system-on-chips," in Global Semiconductors, Vol. 4, pp.94-97, May 2003.
  • Y.Zhao, S.Dey, "Separate Dual Transistor Registor-an Circuit Solution for on-line Testing of Transient Errors in UDSM-IC," in Proc. Intl. On-line Testing Symposium 2003, pp.7-11, Kos Island, Greece, June 2003.
  • X. Bai, L. Chen and S. Dey, "Software-Based Self-Test Methodology for Crosstalk Faults in Processors," in IEEE International High Level Design Validation and Test Workshop, pp.11-16, San Francisco, November 2003.

2002

  • I.Ghosh, K.Sekar, V.Boppana, "Design for Verification at the Register Transfer Level", in Intl. Conf. on VLSI Design/ASP-DAC, pp.420-425, Bangalore, January 2002.
  • A.Krstic, L.Chen, W.-C.Lai, K.-T.Cheng, S.Dey, "Embedded Software-Based Self-Test for Programmable Core-Based Designs," IEEE Design and Test of Computers, vol.19, no.4, July 2002, pp.18-27.
  • A.Krstic, L.Chen, W.-C.Lai, K.-T.Cheng, S.Dey, "Embedded Software-Based Self-Testing for SoC Design," in Proc. Design Automation Conf., New Orleans, June 2002, pp.355-360.
  • K.Sekar, S.Dey, "LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and Interconnects," in Proc. VLSI Test Symposium, Monterey, May 2002.
  • Y.Zhao, L.Chen, S.Dey, "On-line Testing for Multi-source Noise-induced Errors in System-on-Chip Interconnects and Buses," in Proc. Intl. Test Conference, pp.491-499, Baltimore, October 2002.
  • L.Chen, S.Dey, "Software-Based Diagnosis for Processors," in Proc. Design Automation Conf., pp.259-262, New Orleans, June 2002.
  • L.Chen, X.Bai, S.Dey, "Testing for interconnect crosstalk defects using on-chip embedded processor cores," Journal of Electronic Testing: Theory and Applications, vol.18, no.4, August 2002, pp. 529-538.

2001

  • P.Dasgupta, P.P.Chakrabarti, A.Nandi, K.Sekar, A.Chakrabarti, "Abstraction of Word-level Linear Arithmetic Functions from Bit-level Component Descriptions," in Design, Automation, and Test in Europe, pp.4-8, Munich, March 2001.
  • X.Bai, S.Dey, "High-level Crosstalk Defect Simulation for System-on-Chip Interconnects", in Proc. VLSI Test Symposium, Los Angeles, April 2001. pp. 169-175
  • L.Chen, S.Dey, "Software-Based Self-Testing Methodology for Processor Cores," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol.20, no.3, pp.369-380, March 2001.
  • L.Chen, X.Bai, S.Dey, "Testing for interconnect crosstalk defects using on-chip embedded processor cores," in Proc. Design Automation Conf., Las Vegas, June 2001.

2000

  • Y.Zhao, S.Dey, "Analysis of Interconnect Crosstalk Defect Coverage of Test", in Proc. Intl. Test Conference, Atlantic City, October 2000.
  • L.Chen, S.Dey, "DEFUSE: A Deterministic Functional Self-Test Methodology for Processors," in Proc. VLSI Test Symposium, Montreal, April 2000.
  • L.Chen, S.Dey, P.Sanchez, K.Sekar, Y.H.Chen, "Embedded Hardware and Software Self-Testing Methodologies for Processor Cores," in Proc. Design Automation Conf., Los Angeles, June 2000.
  • D.Panigrahi, C.Taylor, S.Dey, "Interface Based Hardware/Software Validation of a System-on-Chip,", in Proc. High-Level Design Validation and Test Workshop (HLDVT), pp.53-58, November 2000.
  • X.Bai, S.Dey, J.Rajski, "Self-Test Methodology for At-Speed Test of Crosstalk in Chip Interconnects", in Proc. Design Automation Conf., Los Angeles, June 2000. pp. 619-24
  • K-T.Cheng, S.Dey, M.Rodgers, K.Roy, "Test Challenges for Deep Sub-Micron Technologies", in Proc. Design Automation Conf., Los Angeles, June 2000.
  • S.Dey, P.Sanchez, D.Panigrahi, L.Chen, C.Taylor, K.Sekar, "Using a Soft Core in a SOC Design: Experiences with PicoJava,", IEEE Design and Test of Computers, vol.17, no.3, pp.60-71, July-September 2000.

1999

  • L.Chen, S.Dey, "A Deterministic Functional Self-Test Methodology for Processors," in Proc. Intl. High-Level Design Validation and Test Workshop, San Diego, November 1999.
  • M.Cuviello, S.Dey, X.Bai, Y.Zhao, "Fault Modeling and Simulation for Crosstalk in System-on-Chip Interconnects", in Proc. Intl. Conf. on Computer-Aided Design, San Jose, November 1999. pp.297-303.
  • Chong Zhao, Yi Zhao, Sujit Dey, "An Intelligent Robustness Insertion Methodology for Optimal Transient Error Tolerance", to appear in IEEE transaction on Very Large Scale Integration Systems. 
  • Chong Zhao, Xiaoliang Bai, Sujit Dey, "Efficient transient error effects in digital nanometer circuits," to appear in IEEE Transactions on Reliability.