Vehicular Edge Computing

Overview
Emerging connected and autonomous vehicles involve complex applications requiring not only optimal computing resource allocations but also efficient computing architectures. We investigate the critical performance metrics required for emerging vehicular computing applications and develop algorithms for optimal choices to satisfy the static and dynamic computing requirements in terms of the performance metrics. Employing the edge computing architectures for vehicular computing, we are developing different task partitioning and task offloading strategies.

Performance metrics

Designing optimal computing architecture for new vehicles
Since future vehicles will have a widely varying set of capabilities and requirements, an important question comes up: what is the optimal computing architecture for a particular vehicle class. For example, given a number of camera sensors that need to be supported for a vehicle, and hence the number of machine vision (e.g., object detection and tracking) instances that need to be executed simultaneously, and the desired latencypower requirements of the instances, what may be the optimal computing architecture (number of CPU/GPU cores and their frequencies) that can satisfy the capability and the requirements.
We explore the above question by conducting a preliminary experiment using an Nvidia Jetson Tx2 board to execute multiple SSD MobileNet v2 (object detection) instances, corresponding to the number of desired cameras for the vehicle, instances. The profiled relationship between the average inference time, capability, and the chosen architecture on Nvidia Jetson Tx2 board is shown below (left). In addition, the power consumption for running a variation of SSD MobileNet v2 instances on Nvidia Jetson Tx2 is shown by the right figure.
The data presented in the above figures show the possibility of developing models to estimate inference time and power consumption based on given requirements (instances) and architecture choices (number of cores, type of cores and frequency). Moreover, the models constructed can be used to help identify an optimal architecture for given capabilities and performance requirements of a set of vehicle applications. Below is an example of available architectures when the performance requirements are using 5 cameras and thereby 5 object detection instances, with maximum average inference time requirement of 0.08 s. Among all the architectures in Table II, if the objective is to minimize the power consumption, then the optimal architecture will be using 3 CPU cores at 1.267 GHz clock frequency, as the row highlighted shows.
Following the same method, we can derive the following, which shows the optimal computing architecture, including various GPU clock frequency, for different capabilities to 1) minimize average inference time under the 10 W power consumption constraint, and 2) minimize power consumption while satisfying the 0.08s average inference time constraint. The optimal system architecture is shown in the format of: (Number of CPU cores, CPU clock frequency), (GPU clock frequency). The results show the tradeoff between changing the number of CPU cores as well as CPU and GPU clock frequencies to achieve the required objective.

Collaborative vehicular edge computing

Endtoend Latency in different Offloading Strategies

This material is partially funded by the National Science Foundation under Grant No. CNS  1619184 . Any opinions, findings, and conclusions or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the views of the National Science Foundation. This project is also partially funded by UCSD Center for Wireless Communications, and the UCSD Smart Transportation Innovation Program (STIP) 
Associated Publications