Validation and Test of Nanometer SoCs

Interconnect Coupling-Aware Driver Modeling in Static Noise Analysis for Nanometer Circuits,

admin — Wed, 12 Nov 2025 19:25:14 +0000

Interconnect Coupling-Aware Driver Modeling in Static Noise Analysis for Nanometer Circuits, admin Wed, 11/12/2025 - 11:25

Publication Info

Xiaoliang Bai, Rajit Chandra, Sujit Dey and P. V. Srinivas, "Interconnect Coupling-Aware Driver Modeling in Static Noise Analysis for Nanometer Circuits," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 23, NO. 8, August 2004. pp. 1256~1263.

Publication Year

2004

Publication Area

Validation and Test of Nanometer SoCs

Software-Based Self-Test Methodology for Crosstalk Faults in Processors,

admin — Wed, 12 Nov 2025 19:24:46 +0000

Software-Based Self-Test Methodology for Crosstalk Faults in Processors, admin Wed, 11/12/2025 - 11:24

Publication Info

X. Bai, L. Chen and S. Dey, "Software-Based Self-Test Methodology for Crosstalk Faults in Processors," in IEEE International High Level Design Validation and Test Workshop, pp.11-16, San Francisco, November 2003.

Publication Year

2003

Publication Area

Validation and Test of Nanometer SoCs

Abstraction of Word-level Linear Arithmetic Functions from Bit-level Component Descriptions,

admin — Wed, 12 Nov 2025 19:23:20 +0000

Abstraction of Word-level Linear Arithmetic Functions from Bit-level Component Descriptions, admin Wed, 11/12/2025 - 11:23

Publication Info

P.Dasgupta, P.P.Chakrabarti, A.Nandi, K.Sekar, A.Chakrabarti, "Abstraction of Word-level Linear Arithmetic Functions from Bit-level Component Descriptions," in Design, Automation, and Test in Europe, pp.4-8, Munich, March 2001.

Publication Year

2001

Publication Area

Validation and Test of Nanometer SoCs

Fault Modeling and Simulation for Crosstalk in System-on-Chip Interconnects

admin — Wed, 12 Nov 2025 19:22:50 +0000

Fault Modeling and Simulation for Crosstalk in System-on-Chip Interconnects admin Wed, 11/12/2025 - 11:22

Publication Info

M.Cuviello, S.Dey, X.Bai, Y.Zhao, "Fault Modeling and Simulation for Crosstalk in System-on-Chip Interconnects", in Proc. Intl. Conf. on Computer-Aided Design, San Jose, November 1999. pp.297-303.

Publication Year

1999

Publication Area

Validation and Test of Nanometer SoCs

Constraint-Aware Robustness Insertion for Optimal Noise-Tolerance Enhancement in VLSI Circuits,

admin — Wed, 12 Nov 2025 19:18:05 +0000

Constraint-Aware Robustness Insertion for Optimal Noise-Tolerance Enhancement in VLSI Circuits, admin Wed, 11/12/2025 - 11:18

Publication Info

Chong Zhao, Yi Zhao, Sujit Dey, "Constraint-Aware Robustness Insertion for Optimal Noise-Tolerance Enhancement in VLSI Circuits," in Proceedings of 42nd Design Automation Conference, pp. 190-195, June 2005, Anaheim, California, USA.

Publication Year

2005

Publication Area

Validation and Test of Nanometer SoCs

Soft Spot Analysis: A Scalable Methodology Targeting Compound Noise Effects in Nano-meter Circuits

admin — Wed, 12 Nov 2025 19:17:34 +0000

Soft Spot Analysis: A Scalable Methodology Targeting Compound Noise Effects in Nano-meter Circuits admin Wed, 11/12/2025 - 11:17

Publication Info

Chong Zhao, Xiaoliang Bai, Sujit Dey, "Soft Spot Analysis: A Scalable Methodology Targeting Compound Noise Effects in Nano-meter Circuits", IEEE Design & Test of Computers, VOL. 22, NO. 4, July-Aug. 2005, pp. 362-375.

Publication Year

2005

Publication Area

Validation and Test of Nanometer SoCs

High-level Crosstalk Defect Simulation Methodology for System-on-Chip Interconnects,

admin — Wed, 12 Nov 2025 19:17:06 +0000

High-level Crosstalk Defect Simulation Methodology for System-on-Chip Interconnects, admin Wed, 11/12/2025 - 11:17

Publication Info

Xiaoliang Bai, Sujit Dey, "High-level Crosstalk Defect Simulation Methodology for System-on-Chip Interconnects," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol 23, NO. 9, September 2004. pp. 1355~1361.

Publication Year

2004

Publication Area

Validation and Test of Nanometer SoCs

A Scalable Soft Spot Analysis Methodology for Compount Noise Effects in Nano-meter Circuits

admin — Wed, 12 Nov 2025 19:10:11 +0000

A Scalable Soft Spot Analysis Methodology for Compount Noise Effects in Nano-meter Circuits admin Wed, 11/12/2025 - 11:10

Publication Info

Chong Zhao, Xiaoliang Bai, Sujit Dey, "A Scalable Soft Spot Analysis Methodology for Compount Noise Effects in Nano-meter Circuits", DAC'04, San Diego, California, June 7-11, 2004.

Publication Year

2004

Publication Area

Validation and Test of Nanometer SoCs

On-line testing of multi-source noise-induced errors on the interconnects and buses of system-on-chips

admin — Wed, 12 Nov 2025 19:09:32 +0000

On-line testing of multi-source noise-induced errors on the interconnects and buses of system-on-chips admin Wed, 11/12/2025 - 11:09

Publication Info

Y. Zhao, L. Chen, S. Dey, "On-line testing of multi-source noise-induced errors on the interconnects and buses of system-on-chips," in Global Semiconductors, Vol. 4, pp.94-97, May 2003.

Publication Year

2003

Publication Area

Validation and Test of Nanometer SoCs

ATPG for Crosstalk using Hybrid Structural SAT,

admin — Wed, 12 Nov 2025 19:09:07 +0000

ATPG for Crosstalk using Hybrid Structural SAT, admin Wed, 11/12/2025 - 11:09

Publication Info

X.Bai, S.Dey, A.Krstic, "ATPG for Crosstalk using Hybrid Structural SAT," in Intl. Test Conference, pp.112-121, Charlotter, Oct. 2003.

Publication Year

2003

Publication Area

Validation and Test of Nanometer SoCs