PhD Student
Li Chen
Krishna Sekar

Visiting Researcher
Dr. Angela Krstic

Modern VLSI technology enables the chip-level integration of large systems, comprising of embedded processors, DSPs, and other complex components. The gigascale system-level integration, while benefiting the system design process in several ways, poses many challenges for testing. For components deeply embedded inside the system, test pattern application and test response propagation are difficult. Moreover, the need for at-speed testing imposes an ever-increasing requirement on the speed and accuracy of external testers. According to the 1997 Semiconductor Industry Association Roadmap, if current semiconductor testing technologies are continued, the test equipment cost can rise toward $20 million, and at-speed testing of GHz range chips will result in unacceptably high yield loss of 48% by 2012. To ensure the economic viability of the industry to manufacture high-performance, heterogenous system chips in the next decade, radically new testing technologies are needed.

To alleviate the burden on external testers, our research goal is to develop models, techniques and tools that enables self-test of system-on-chips. While Built-in Self-Test techniques have been successful for structured components like embedded memory, application to complex logic components like processors has been elusive due to prohibitive overhead and low fault coverage. We are developing novel self-test techniques which utilize the programmability of the components of a system-on-chip. For processor cores, the proposed technique involves on-chip test pattern generation, delivery, and response analysis, for each module of the core, using the instruction set of the processor. The resulting "self-test program", when executed by the processor core, will ensure high fault coverage of the core. At the system level, our test methodology involves using the programmability of the processor cores to generate and apply required test patterns to the other components of the chip.

This project is part of the nation-wide GigaScale Research Center recently formed by the Semiconductor Industry Association, Sematech, and DARPA.

• L. Chen, S. Ravi, A. Raghunathan, and S. Dey, "A scalable software-based self-test methodology for programmable processors," Proc. 40th Design Automation Conf., Anaheim, CA, June 2003, pp. 548-553. (Best Paper Award Candidate) (pdf)
• Y. Zhao, L. Chen, and S. Dey, "On-line Testing for Multi-source Noise-induced Errors in System-on-Chip Interconnects and Buses," IEEE Proceedings of International Testing Conference, Baltimore, MD, October 2002, pp. 491-499. (pdf)
• A. Krstic, L. Chen, W.-C. Lai, K.-T. Cheng, and S. Dey, "Embedded Software-Based Self-Test for Programmable Core-Based Designs," IEEE Design and Test of Computers, vol.19, (no.4), July 2002, pp. 18-27. (pdf)
• L. Chen, X. Bai, and S. Dey, "Testing for interconnect crosstalk defects using on-chip embedded processor cores," Journal of Electronic Testing: Theory and Applications, vol.18, (no.4), August 2002, pp. 529-538. (pdf)
• L. Chen and S. Dey, "Software-based diagnosis for processors," Proc. 39th Design Automation Conf., New Orleans, LA, June 2002, pp. 259-262. (pdf)
• A. Krstic, L. Chen, W.-C. Lai, K.-T. Cheng, and S. Dey, "Embedded Software-Based Self-Testing for SoC Design," Proc. 39th Design Automation Conf., New Orleans, LA, June 2002, pp. 355-360. (pdf)
• K. Sekar and S. Dey, "LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and Interconnnects," Proc. 20th IEEE VLSI Test Symposium, May 2002. (pdf)
• L. Chen, X. Bai, and S. Dey, "Testing for interconnect crosstalk defects using on-chip embedded processor cores," Proc. 38th Design Automation Conference, Las Vegas, NV, June 2001, pp. 317-322. (pdf)
• L. Chen and S. Dey, "Software-based self-testing methodology for processor cores," IEEE Trans. Computer-Aided Design, vol.20, (no.3), March 2001, pp. 369-380. (pdf)
• S. Dey, P. Sanchez, D. Panigrahi, L. Chen, C. Taylor, and K. Sekar, "Using a Soft Core in a SOC Design: Experiences with picoJava," IEEE Design and Test of Computers, vol.17, (no.3), July-September 2000, pp. 60 - 71. (pdf)
• Li Chen, Sujit Dey, Pablo Sanchez, Krishna Sekar, and Ying Chen, "Embedded Hardware and Software Self-Testing Methodologies for Processor Cores," Proceeding of the 37th Design Automation Conference, Los Angeles, CA, June 2000, pp. 625 - 630. (pdf)
• Li Chen and Sujit Dey, "DEFUSE: A Deterministic Functional Self-Test Methodology for Processors," Proceedings of the 18th IEEE VLSI Test Symposium 2000, Montreal, Canada, April 2000, pp. 255 - 262. (pdf)
• Li Chen and Sujit Dey, "A Deterministic Functional Self-Test Methodology for Processors," IEEE International High Level Design Validation and Test Workshop 1999, San Diego, CA, Nov. 1999, pp. 17 - 22. (pdf)

• "Embedded Hardware and Software Self-Testing Methodologies for Processor Cores," presented at DAC 2000, Los Angeles, CA, June 2000. (pdf coming soon...)
• "DEFUSE: A Deterministic Functional Self-Test Methodology for Processors," presented at VTS 2000, Montreal, Canada, April 2000. (pdf coming soon...)
• ITSW 2000, Santa Barbara, CA, March 2000. (pdf coming soon...)
• "Experience with Synthesis, Simulation, Test, and Integration of PicoJava Processor Core," presented at ITC'99, Sept. 1999 (pdf)
• "A Deterministic Functional Self-Test Methodology for Processors," presented at HLDVT'99, Nov. 1999 (pdf)
• "Design Test," presented at MARCO kick-off meeting, San Jose, Dec. 9, 1998 (pdf)
• "System Chip Test Challenges: Are There Solutions Today?," presented at the 35th Design Automation Conference, June 1998 (pdf)

• Abstract published in the 2001 JSOE Research Review (pdf)
• Abstract published in the 2000 JSOE Research Review (pdf)
• Abstract published in the 1999 JSOE Research Review (ps)

Gigascale Silicon Research Center (GSRC)
GSRC Test Thrust
 

Embedded System Design Automation and Test Group
PicoJava Processor Core
ACS's website on Mentor tools
Conference deadlines

The following links are password protected:
PicoJava: PicoJava verification status . . . Testing PicoJava FPU . . . PicoJava links
PARWAN: PARWAN processor (preliminary documenation) . . . Testing PARWAN (for ece260c students)
DLXS: Testing of the DLXS processor . . . Testing DLXS (for ece260c students)
Software-based testing: For stuck-at faults (Test program synthesis). . . For crosstalk faults
Xiaoliang Bai's research page
GSRC internal documents and presentations
Bibliography
Bookmarks to EE articles
Internal talks