PhD Student
Krishna Sekar

Conventional testing leads to excessive power consumption in the test mode. This is because testing causes the maximal switching of nodes by the test vectors and also since there is a low correlation between successive test vectors. Our experiments show that power consumed during testing can be as high as 2X times the power in the normal mode of operation of the circuit. This leads to new test related costs in IC chip manufacture which include need for expensive packaging, power grid routing, expensive cooling equipment, potential damage to the chip etc.

Our research goal is to develop low-power self-test methods for System-on-Chip components and interconnects. We are developing a power-aware, software-based, self-test methodology for testing embedded components. We are also developing low-cost, low-power on-chip hardware self-test structures for testing the logic components as well as the system interconnects.

This project is part of the nation-wide GigaScale Research Center recently formed by the Semiconductor Industry Association, Sematech, and DARPA.

• Low Power Testing of VLSI circuits - A review : Group Meeting Presentation (ppt)

Gigascale Silicon Research Center (GSRC)
GSRC Test Thrust
 

Embedded System Design Automation and Test Group